UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 55891: Kintex-7 FPGA Embedded Kit - MIG 7 Series v1.9 DDR3/DDR2 PRBS Calibration results are not applied

AR# 55891

Kintex-7 FPGA Embedded Kit - MIG 7 Series v1.9 DDR3/DDR2 PRBS Calibration results are not applied

Description

The MIG 7 Series DDR3/DDR2 design performs Read Leveling Calibration followed by PRBS Read Leveling Calibration to fine tune the centering of the read capture clock. In the MIG 7 Series v1.9 rtl ONLY, a specific line of code is incorrectly commented out, causing the results of the PRBS Read Leveling Calibration stage (increments and decrements to the Phaser_IN blocks) to not be applied as if the stage of calibration did not run. Calibration will not fail, but the fine tuned adjustments found during PRBS Read Leveling will not be applied. This can cause read data errors post calibration. Manual modification is required within the MIG 7 Series v1.9 rtl.

This is described in (Xilinx Answer 55531).

Solution

If you are running the Kintex-7 FPGA Embedded Kit Targeted Reference Design, you may notice behavior as described above.
If that is the case, to work around this issue please perform the following for both BIST and Video Demo designs for the Kintex-7 FPGA Embedded Kit:

1. Open XPS project of the design
2. In the system assembly view of the XPS GUI, right click on axi_7series_ddrx (DDR3_SDRAM) IP and select option Make This IP Local.
3. Navigate to local pcore directory of the XPS project
4. Locate line 228 within the "../sources_1/edk/MicroBlaze_ProcessorSubSystem/pcores/axi_7series_ddrx_v1_08_a/hdl/verilog/mig_7series_v1_9_ddr_phy_prbs_rdlvl.v" module:
     //assign pi_stg2_prbs_rdlvl_cnt = prbs_dqs_cnt_r;
5. Uncomment this statement:
     assign pi_stg2_prbs_rdlvl_cnt = prbs_dqs_cnt_r;
6. Generate the bitstream again with this rtl change

The bit files generated to include the above mentioned workaround, for both BIST and Video Demo design, are attached to this answer record for quick reference.

BIST_download.bit
VIDEO_DEMO_download.bit

Attachments

Associated Attachments

Name File Size File Type
BIST_download.bit 10 MB BIT
VIDEO_DEMO_download.bit 10 MB BIT

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
52970 Kintex-7 FPGA Embedded Kit - Known Issues and Release Notes Master Answer Record N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
55531 Design Advisory for MIG 7 Series v1.9 DDR3/DDR2 - PRBS Calibration results are not applied (RTL Update Required) N/A N/A
AR# 55891
Date 05/08/2013
Status Active
Type General Article
Boards & Kits
  • Kintex-7 FPGA Embedded Kit
Page Bookmarked