The MIG 7 Series DDR3/DDR2 design performs Read Leveling Calibration followed by PRBS Read Leveling Calibration to fine tune the centering of the read capture clock. In the MIG 7 Series v1.9 rtl ONLY, a specific line of code is incorrectly commented out, causing the results of the PRBS Read Leveling Calibration stage (increments and decrements to the Phaser_IN blocks) to not be applied as if the stage of calibration did not run. Calibration will not fail, but the fine tuned adjustments found during PRBS Read Leveling will not be applied. This can cause read data errors post calibration. Manual modification is required within the MIG 7 Series v1.9 rtl.
This is described in (Xilinx Answer 55531).
Name | File Size | File Type |
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BIST_download.bit | 10 MB | BIT |
VIDEO_DEMO_download.bit | 10 MB | BIT |
Answer Number | Answer Title | Version Found | Version Resolved |
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52970 | Kintex-7 FPGA Embedded Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
55531 | Design Advisory for MIG 7 Series v1.9 DDR3/DDR2 - PRBS Calibration results are not applied (RTL Update Required) | N/A | N/A |
AR# 55891 | |
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Date | 05/08/2013 |
Status | Active |
Type | General Article |
Boards & Kits |