AR# 55899


7 Series Integrated Block for PCI Express v1.9 - The core does not link train when selecting 125 MHz as the reference clock frequency


Version Found: v1.9
Version Resolved and other Known Issues: See (Xilinx Answer 40469)

The core does not link train if you generate the 7 Series Integrated Block for PCI Express v1.9 core with a 125 MHz reference clock frequency.


This is a known issue to be fixed in a future release of the core.

To work around this issue, replace pcie_7x_v1_9_pipe_clock.v ( <core_name_pipe_clock.v>) in the 'Source' directory with the file attached at the end of this answer record after renaming the file according to the core name.

For asynchronous clocking, set PCIE_ASYNC_EN parameter to 'TRUE'.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/17/2013 - Initial release


Associated Attachments

Name File Size File Type
pcie_7x_v1_9_pipe_clock.v 20 KB V

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AR# 55899
Date 08/14/2013
Status Active
Type General Article
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