The MIG 7 Series DDR3/DDR2 design performs Read Leveling Calibration followed by PRBS Read Leveling Calibration to fine tune the centering of the read capture clock. In the MIG 7 Series v1.9 rtl ONLY, a specific line of code is incorrectly commented out causing the results of the PRBS Read Leveling Calibration stage (increments and decrements to the Phaser_IN blocks) to not be applied as if the stage of calibration did not run. Calibration will not fail, but the fine tuned adjustments found during PRBS Read Leveling will not be applied. This can cause read data errors post calibration. Manual modification is required within the MIG 7 Series v1.9 rtl.
This is described in (Xilinx Answer 55531).
If you are running the Kintex-7 FPGA Connectivity Kit Targeted Reference Design, you may notice behavior as described above.
If that is the case, to work around this issue please perform the following for the Connectivity Targeted Reference Design for the Kintex-7 FPGA Connectivity Kit:
1. Browse to k7_connectivity_trd_v1_4/design/implement/vivado folder
2. Run vivado -source k7_conn_gui.tcl
3. Click on Open Elaborated Design. This step will generate MIG IP
4. Browse to the vivado_run/k7_connectivity_trd.srcs/sources_1/ip/mig_axi_mm/mig_axi_mm/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_prbs_rdlvl.v module
5. Locate line 228 within the file mig_7series_v1_9_ddr_phy_prbs_rdlvl.v
//assign pi_stg2_prbs_rdlvl_cnt = prbs_dqs_cnt_r;
assign pi_stg2_prbs_rdlvl_cnt = prbs_dqs_cnt_r;
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