My design has failed with the following placement error:
Phase 7.1 IO & Clk Placer & Init
ERROR: [Place 30-648] Unroutable placement for BUFHCEs with slice-type drivers.
ura_clk_blk/cbuf_c192/sd1_i_1__14 (LUT3.O) is not placed
ura_clk_blk/cbuf_c192/sd1_i_1 (LUT3.O) is not placed
ura_clk_blk/cbuf_c61/sd1 (BUFH.I) is provisionally placed by clockplacer on BUFHCE_X1Y82
ura_clk_blk/cbuf_c62/sd1 (BUFH.I) is provisionally placed by clockplacer on BUFHCE_X1Y89
Resolution: A maximum of 2 BUFHCEs with slice-type drivers can be placed in a clock region for the design to be routable.
Each clock region has 12 BUFHs available, so why does this message say "maximum of 2 BUFHCEs with slice-type drivers can be placed in a clock region"?
This message refers to the BUFHCE sites which are a clock buffers normally used for global clocks to enter a clock region and gain access to the clock tree within the clock region. The router will use the BUFHCE resources automatically (via a route-thru) if no instantiated BUFHCE is involved. There are 12 BUFHCE sites per clock region which normally allows for 12 global clock nets to enter a clock region. Occasionally a designer will want to give a non-global net access to a BUFHCE so that it can also make use of the clock tree internal to the clock region. This is done by instantiating a BUFHCE component driven by the desired logic. Each time this is done, one less global clock can enter the clock region. Additionally, since there is limited switchbox connectivity from the general fabric to the BUFHCE sites, only two such connections can be made per clock region. This is what is meant by "slice type drivers of BUFHCEs" and why they must be floorplanned so that there are no more than two per clock region.