AR# 55991

14.x PlanAhead - Clock Interaction Report is not completely clear how it treats user TIG'ed paths as unconstrained


The Clock Interaction Report in the PlanAhead tool treats the user TIG'ed paths as unconstrained. Following are some examples:

  • When there is no constraint on the paths between asynchronous clock domains, the cell is red which means unconstrained.
  • When all paths between asynchronous clock domains are covered by TIG constraints, the cell is still red. Although it is labeled "user ignored paths," the user has no idea if they are "constrained" or not.
  • When some paths are covered by FROM-TO constraints and the other paths are covered by TIG constraints, the cell is yellow. In fact, all paths are explicitly constrained. However, "yellow" tells the user that they are partially constrained which is confusing.


The PlanAhead version of the clock interaction report has some limitations, which are mentioned above. The Clock Interaction Report in the Vivado tool is clearer with additional cell colors and categories that make more sense. It indicates if two pairs of clocks are fully constrained, fully unconstrained, fully false path, partial false path, or MAXDELAY DATAPATHONLY.

Note: In the Vivado tool, two clocks are treated as related by default unless they are explicitly specified as asynchronous by set_clock_groups.

In the PlanAhead tool, use report_timing or Timing Analyzer (TRCE) to help to determine the constraints coverage.

AR# 55991
Date 10/09/2013
Status Active
Type General Article