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AR# 56057

Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.4 [Vivado 2012.4] - Core may reply with an incorrect value for the Configuration Read Request to the Device ID

Description

Version Found: v1.4
Version Resolved and other Known Issues: See (Xilinx Answer 47441)

The core might reply with an incorrect Device ID when reading the Device ID of the Virtex-7 FPGA Gen3 Integrated Block for PCI Express v1.4 core with a Configuration Read Request.

Solution

The following reset signals coming out of pcie_init_ctrl_7vx.v are susceptible to glitches that could induce the core to return an incorrect Device ID:

reset_n_o           
pipe_reset_n_o      
mgmt_reset_n_o      
mgmt_sticky_reset_n_o

To work around this issue, modify pcie_init_ctrl_7vx.v file as described below:

FROM:

  assign reset_n_o                                = reg_reset_n_o;
  assign pipe_reset_n_o                     = reg_pipe_reset_n_o;
  assign mgmt_reset_n_o                  = reg_mgmt_reset_n_o;
  assign mgmt_sticky_reset_n_o      = reg_mgmt_sticky_reset_n_o
TO:
  reg                 regff_mgmt_reset_n_o = 1'b0;
  reg                 regff_mgmt_sticky_reset_n_o = 1'b0;
  reg                 regff_reset_n_o = 1'b0;
  reg                 regff_pipe_reset_n_o = 1'b0;
 

  // Register signals
  always @(posedge clk_i) begin
    regff_mgmt_reset_n_o                 <= reg_mgmt_reset_n_o;
    regff_mgmt_sticky_reset_n_o    <= reg_mgmt_sticky_reset_n_o;
    regff_pipe_reset_n_o                   <= reg_pipe_reset_n_o;
    regff_reset_n_o                             <= reg_reset_n_o;
   end
 
  assign reset_n_o                             = regff_reset_n_o;
  assign pipe_reset_n_o                   = regff_pipe_reset_n_o;
  assign mgmt_reset_n_o                = regff_mgmt_reset_n_o;
  assign mgmt_sticky_reset_n_o   = regff_mgmt_sticky_reset_n_o;

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
05/18/2013 - Initial Release

Linked Answer Records

Master Answer Records

AR# 56057
Date Created 05/17/2013
Last Updated 05/17/2013
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2012.4
IP
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)