AR# 5609


M1.5i Virtex VHDL simprim model incorrect for SRL16, SRL16_1, SRL16E, and SRL16E_1 models


Keywords: Simprims, VHDL, models, SRL16, 1.5i

Urgency: Standard

General Description:
The VHDL simprim models for M1.5i incorrectly simulate the SRL16,
SRL16_1, SRL16E, and SRL16E_1 models. The problem is found in the
address pins on the shift register. The pins are simulated in reverse
order. For example, if you assign A3=1, A2=0, A1=0, and A0=0, which is
a 9-bit stage, it is not and is really a 2-bit stage and the pins are
A3=0, A2=0, A1=0, and A0=1.


The VHDL library needs to be modified. The file is found at:

Make the following modification to the SRL16 model:
ADDRESS := (A3_ipd, A2_ipd, A1_ipd, A0_ipd);
if (VALID_ADDR) then


where ADDRESS is defined as std_logic_vector(3 downto 0);

The vhd file will need to be re-compiled for the changes to take

This is fixed in Xilinx 2.1i
AR# 5609
Date 04/03/2000
Status Archive
Type General Article
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