AR# 56113

Design Advisory for Spartan-6 BUFIO2, DIVIDE = 2 Issue


In Spartan-6 FPGA, the BUFIO2 using the DIVIDE(2) applications can occasionally enter a stuck state. Hence, it is not supported and an alternative implementation needs to be used.


The DIVCLK and SERDESSTROBE outputs will no longer operate when in the stuck state. The BUFIO2 remains in the stuck state until reconfigured. The IOCLK is not dependent on the state machine and will continue to operate.

In certain configurations, the BUFIO2 can potentially enter the stuck state due to glitches on the clock input of the BUFIO2. These glitches can be caused by a number of sources including unstable clocks, floating inputs, or the FPGA configuration start-up conditions. Even with a known clean clock at the inputs of the Spartan-6 device, the BUFIO2 can still go into the stuck state due to internal glitches from FPGA configuration/start-up conditions.

DRC Information

If using the DIVIDE = 2, (starting in ISE Design Suite 14.6) you will see a DRC error that says: Element BUFIO2_XY has invalid setting of divide by 2. This setting is not supported. For more information, see (Xilinx Answer 56113).
Again, this above DRC will be implemented in ISE Design Suite 14.6.

Alternative Solutions

To avoid using the BUFIO2, DIVIDE(2) setting, a number of standard ways of reducing clock frequencies are listed here. This is by no means a complete list, but is being supplied to highlight some of the more common solutions. In Figure 1a: Failing Clock Generation with BUFIO2, DIVIDE(2), the BUFIO2 is being used to divide FIN by 2.

Dividing clocks internal to FPGAs is commonly done using DCMs and PLLs; these techniques still apply and can be used to avoid the failing BUFIO2 conditions. Please take into account the DCM/PLL requirements must still be met. If phase alignment is a design requirement, the BUFIO2FB feedback buffer should additionally be used as shown in DCM Clock Divider. The PLL can similarly be used.

For customers that were using a divided clock to create an external clock output, an OSERDES solution can be safely used because the DIVIDE(4) is being used (Figure 1b) as shown in Alternative Clock Generation with BFUIO2, DIVIDE(4). Please note the IOCLK from the BUFIO2 can only route to I/Os within the same half bank. Routing restrictions may apply.

When using SDR, data is driven out on every rising edge of the IOCLK (SDR) as shown in Timing Waveform for OSERDES2 SDR Clock Generation. As a result, driving the data pattern of 1010 will mean that every clock edge (IOCLK(SDR) the data polarity flips. This means that the clock patterns data rate will match the IOCLKs frequency. But, because the goal is to generate a clock data pattern of 2 bits (1 and 0), this means that the clock pattern at the pin will appear as FIN/2.

DataRate SDR_1010 = FIN

Data pattern 1/1/0/0 generates clock pulse with data rate because the clock pattern repeats every two data bits (1,0).

FSDR_1010= DataRate SDR_1010 / 2 = FIN / 2

Alternatively, for customers that want to use DDR data rates, the second OSERDES2 option can add the doubler mode for the OSERDES2 as shown in Figure 1c. The same BUFIO2 routing restrictions apply but because the USE_DOUBLER(TRUE) is being used, please be aware that additional routing restrictions will apply; specifically, the requirement of a second BUFIO2 (I_INVERT) which has dedicated placement as outlined in UG382. Additionally, the USE_DOUBLER(TRUE) requires a second routing (for the BUFIO2_2CLK) that is not available for the GTP clocks. As a result, this solution would only be viable when routing from global clock pins.

When using the OSERDES2 with DATA_RATE (DDR), please note that the data patterns are different (1100). This is the result of how the clocks are being generated. Two clocks are now being driven, CLK0, CLK1 as shown in Timing Waveform for OSERDES2 DDR Clock Generation. In this situation, CLK0 drives out every other data bit (e.g., D0, D2 for DIVIDE(4)). But, because DDR mode is being used, there is now a second clock source driven by the second BUFIO2, I_INVERT(TRUE) driving to CLK1. As shown, IOCLK1 is the inverted version of IOCLK0 (or phase shifted 180 degrees assuming a perfect 50/50 duty cycle) to create the second clock. IOCLK1 will also drive out the other data bit, D1, D3 for DIVIDE(4) example shown.

DataRate DDR_1100 = FIN * 2

Data pattern 1/1/0/0 generates clock pulse with data rate because it takes 4 data bits (1,1,0,0) to create a single clock pulse.

FDDR_1100 = DataRate DDR_1100 / 4 = FIN * 2 / 4 = FIN / 2

Revision History
05/22/13 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A

Associated Answer Records

AR# 56113
Date 06/13/2013
Status Active
Type Design Advisory