It has been found that the rx_frame_complete flag was inserted incorrectly causing the state machine to transition to an incorrect state. This issue has been fixed in the patch that is attached at the end of this answer record.
To use the patch:
1. Replace the file %XILINX_EDK%\hw\XilinxProcessorIPLib\pcores\axi_ethernet_v3_01_a\hdl\src\verilog\axi_ethernet_v3_01_a_v6_rx_axi_intf.v with the file attached.
2. Clean the generated files and reimplement the design
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