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Below are some issues that might occur when migrating your design from ES to Production silicon.
Main Symptom: At power-up, booting in any boot mode, the JTAG chain does not show the DAP.
Other symptoms: INIT_B goes and stays LOW and iMPACT during Initialize chain returns multiple "Added Device UNKNOWN successfully." Debug Step: Take one Scope capture of VCCMIO, POR_B, SRST_B and PS_CLK (Xilinx Answer 52847) Sequencing for SRST and POR Signals
Other symptoms: INIT_B goes and stays LOW or INIT_B never goes LOW. Debug Step: Take one Scope capture of POR_B, SRST_B PROG_B and INIT_B (Xilinx Answer 56272) PROG_B must be pull-up (HIGH) during boot
Other symptoms: INIT_B never goes LOW. Possible intermittent booting. Debug Step: The system should boot in JTAG mode and PLL bypassed (with MIO = 1) (Xilinx Answer 54195) VCCPLL Sensitivity
Other symptoms: INIT_B never goes LOW. Possible intermittent booting. Debug Step: Take one Scope capture of POR_B, INIT_B and the last PL power supply (Xilinx Answer 63149) Secure Lockdown triggered by PS_POR_B reset sequence
Main Symptom: The system does not boot in QSPI/NAND/SD boot mode
Other symptoms: FSBL hangs during execution (Xilinx Answer 55707) FSBL unable to boot when using 32-bit HP AXI ports