AR# 56195

Design Advisory for Zynq-7000 SoC - Why does a design that worked with ES silicon now fail to boot with Production silicon?

Zynq-7000 SoC production devices have enhanced features and security that resulted in new error checking functions in the production Boot Rom.

As a result, marginal designs that booted in ES might no longer boot with Production silicon.

The following answer records document issues that have been known to exhibit this behavior.

To address all questions related to the Zynq-7000 SoC, please visit the Zynq-7000 SoC Solution Center (Xilinx Answer 52512)

Please review the following documents and answer records to find the differences between Silicon Revisions:

Below are some issues that might occur when migrating your design from ES to Production silicon.

Main Symptom: At power-up, booting in any boot mode, the JTAG chain does not show the DAP.

Other symptoms: INIT_B goes and stays LOW and iMPACT during Initialize chain returns multiple "Added Device UNKNOWN successfully."
Debug Step: Take one Scope capture of VCCMIO, POR_B, SRST_B and PS_CLK
(Xilinx Answer 52847) Sequencing for SRST and POR Signals

Other symptoms: INIT_B goes and stays LOW or INIT_B never goes LOW.
Debug Step: Take one Scope capture of POR_B, SRST_B PROG_B and INIT_B
(Xilinx Answer 56272) PROG_B must be pull-up (HIGH) during boot

Other symptoms: INIT_B never goes LOW. Possible intermittent booting.
Debug Step: The system should boot in JTAG mode and PLL bypassed (with MIO[6] = 1)
(Xilinx Answer 54195) VCCPLL Sensitivity

Other symptoms: INIT_B never goes LOW. Possible intermittent booting.
Debug Step: Take one Scope capture of POR_B, INIT_B and the last PL power supply.
(Xilinx Answer 63149) Secure Lockdown triggered by PS_POR_B reset sequence.

Main Symptom: The system does not boot in QSPI/NAND/SD boot mode

Other symptoms: FSBL hangs during execution
(Xilinx Answer 55707) FSBL unable to boot when using 32-bit HP AXI ports

Was this Answer Record helpful?

Answer Number	Answer Title	Version Found	Version Resolved
52512	Xilinx Zynq-7000 SoC Solution Center	N/A	N/A
52847	Zynq-7000 Board Design - Sequencing for SRST and POR Signals	N/A	N/A
56272	Zynq-7000 SoC - PROG_B must be pullup during BootROM execution in production silicon	N/A	N/A
54195	Design Advisory for Zynq-7000 SoC - VCCPLL Sensitivity	N/A	N/A
63149	Design Advisory for Zynq-7000 SoC: Secure Lockdown triggered by PS_POR_B reset sequence	N/A	N/A
55707	14.5 EDK, Zynq-7000 - FSBL unable to boot when using 32-bit HP AXI ports	N/A	N/A

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