Zynq-7000 SoC production devices have enhanced features and security that resulted in new error checking functions in the production Boot Rom.
As a result, marginal designs that booted in ES might no longer boot with Production silicon.
The following answer records document issues that have been known to exhibit this behavior.
To address all questions related to the Zynq-7000 SoC, please visit the Zynq-7000 SoC Solution Center (Xilinx Answer 52512)
Please review the following documents and answer records to find the differences between Silicon Revisions:
Below are some issues that might occur when migrating your design from ES to Production silicon.
Main Symptom: At power-up, booting in any boot mode, the JTAG chain does not show the DAP.
Main Symptom: The system does not boot in QSPI/NAND/SD boot mode
Answer Number | Answer Title | Version Found | Version Resolved |
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52512 | Xilinx Zynq-7000 SoC Solution Center | N/A | N/A |
52847 | Zynq-7000 Board Design - Sequencing for SRST and POR Signals | N/A | N/A |
56272 | Zynq-7000 SoC - PROG_B must be pullup during BootROM execution in production silicon | N/A | N/A |
54195 | Design Advisory for Zynq-7000 SoC - VCCPLL Sensitivity | N/A | N/A |
63149 | Design Advisory for Zynq-7000 SoC: Secure Lockdown triggered by PS_POR_B reset sequence | N/A | N/A |
55707 | 14.5 EDK, Zynq-7000 - FSBL unable to boot when using 32-bit HP AXI ports | N/A | N/A |
AR# 56195 | |
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Date | 06/13/2018 |
Status | Active |
Type | Design Advisory |
Devices | |
Tools |