We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56205

Clocking - How to connect BUFR to be used in BYPASS mode


Table 2-7 of (UG472) states that the CE and CLR ports of a BUFR "cannot be used in BYPASS mode".

However, if I comment out the CE and CLR inputs in a VHDL design, I receive the following error:

ERROR:HDLCompiler:432 - "test.vhdl" Line 2752: Formal <ce> has no actual or default value.

How should this be handled?


What the Clocking Resources Guide is trying to explain in table 2-7 is that these inputs (CE and CLR) should not be connected to signals that change.

If you do connect them to a signal you will receive the following Map warning which lets you know that these will not be used even though you have connected them:

WARNING:PhysDesignRules:1267 - Issue with pin connections and/or configuration on block:<TESTbufr>:<BUFR_BUFR>.
Useless input. The input pins CE and CLR are not used for BUFR_DIVIDE BYPASS.

The CE and CLR pins should be tied '1' and '0' respectively to avoid both the synthesis error and the Map warning.

AR# 56205
Date 01/14/2016
Status Active
Type General Article
  • ISE
Page Bookmarked