AR# 56214

System Generator for DSP v14.5 - Patch Update for numerous known issues


This answer record contains patch updates for the System Generator for DSP v14.5, which addresses the following issues:

  • Shared memories in user-defined libraries cannot be added to EDK Processor block. See (Xilinx Answer 54609)
  • EDK export flow generates ports which are bit swapped to support legacy PLB endianness. See (Xilinx Answer 53744)
  • Shared Memory block using illegal BRAM WRITE_MODE when dual clocks is enabled. See (Xilinx Answer 56380)
  • Added support for custom definition of AXI Stream Protocol when using custom bus tool. See (Xilinx Answer 56381)

Please note the attached patch is for Windows 64-bit OS only.

These issues are fixed in System Generator 14.6.


Installation and Use:

Prior to installing the update, you must ensure you have installed the ISE Design Suite release of 14.5, as required by the patch. The ISE Design Suite release can be obtained from the following link, if needed:

Install the patch by extracting the contents of the ZIP archive to the root directory of XILINX (Xilinx ISE software installation), or your MYXILINX environment variable. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.

For information on finding the Xilinx install and using the environment variable, see (Xilinx Answer 11630).

For information on using the MYXILINX environment variable, see (Xilinx Answer 2493).

Note: If you do not have write permissions to the Xilinx Install directory, or cannot use the MYXILINX option, you might be required to have a system administrator install the patch.

For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595)



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AR# 56214
Date 06/13/2013
Status Active
Type General Article