AR# 56228

MIG 7 Series RLDRAM II / 3 - "ERROR: [Place 30-109] can occur when generating the MIG IP in batch mode"


Version Found: v1.9.a
Version Resolved: See (Xilinx Answer 54025)

When generating a MIG 7 Series RLDRAM v1.9.a design in batch mode the following error message can occur during implementation:

ERROR: [Place 30-109] The following IOBs have been constrained (LOC constraint) to the I/O bank 33.
They require a voltage reference supply from the VREF pin(s) within the same I/O bank to be available.
The following VREF pins are currently locked and can't be used to supply the necessary reference
IO Standard: SioStd: SSTL12     VREF = 0.6 Termination: 0  TermDir:  In   Bank: 33 Placed GClock :
     List of placed IOBs :
        Term: clk_ref_i

     List of Occupied VREF Sites: 
        VREF Pin: W8 is occupied by term: rldiii_a[12]
        VREF Pin: AE11 is occupied by term: rldiii_a[2]


This is a valid error message as pins cannot be placed on VREF pins when External Vref is used. This can only occur when generating the MIG IP in batch mode.

To work around the issue, you can correct the pin-out violation and then regenerate in MIG batch or GUI mode.

Revision History
06/19/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 56228
Date 09/05/2013
Status Active
Type Known Issues