The simulation failure occurs in the Vivado post-synthesis Verilog model.
The failure can occur in any RACH configuration which uses multiple frequency channels where the Number of Frequency Channels is greater than 5.
The error manifests as an incorrect output on the RACH channel.
The cause of the error is incorrect RAM initialization in the frequency demodulator.
This demodulates the RACH signal incorrectly, creating a failed correlation result.
A suitable workaround is to simulate using either:
For the LogiCORE IP LTE RACH Detector - Release Notes and Known Issues, see (Xilinx Answer 54487).