Open any Zynq design and select both SPI0 and SPI1 to be on EMIO. The Zynq PS clocking Wizard will show the SPI controller frequency @ 0 MHz. Also in Zynq TAB the two SPI via EMIO are marked as RED.
If user runs the Generate Netlist command on the design then platgen crashes out with following error message:
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
make: *** [implementation/system_clock_generator_0_wrapper.ngc] Floating point exception (core dumped)
The crash also occurs on Windows platforms.
This issue occurs in any Zynq 7000 design prepared from XPS 14.5 or XPS 14.6 releases.
To overcome these problems stated above, you can replace the file spi1_preset.xml attached at the end of this answer record in the following build path, then reopen the MIO page and configure it: In a default installation on a computer with a Windows OS, the path is: C:\Xilinx\<ISE_VERSION>\ISE_DS\ISE\data\zynqconfig\spi
In a default installation on a computer with a Windows OS, the path is:
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