UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56271

LogiCORE IP Video Timing Controller v6.0 - Why do I get an CRITICAL WARNING: [Common 17-161] Invalid option value '6.73400 6.73400' specified for 'delay' in Vivado 2013.1 or 2013.2, my clock source is from a clock mux?

Description

Why do I get a CRITICAL WARNING: [Common 17-161] Invalid option value '6.73400 6.73400' specified for 'delay' in Vivado 2013.1 or 2013.2 design tools, my clock source is from a clock mux?

CRITICAL WARNING: [Common 17-161] Invalid option value '6.73400 6.73400' specified for 'delay'. [zynq_base_trd/zynq_base_trd.srcs/sources_1/bd/design_1/ip/design_1_v_tc_1_0/design_1_v_tc_1_0_clocks.xdc:7

Solution

This is because the delay must be determined from the PERIOD of a single clock, but a list of clocks connected to each BUFGMUX is returned.  The user should use the set_case_analysis to select the fastest clock of all BUFGMUXs to be used for timing analysis.  This can be done by using the following format.

    create_clock -period 10.0 [get_ports CLK_A]
    create_clock -period 15.0 [get_ports CLK_B]
    set_case_analysis 0 [get_ports SEL]

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54541 LogiCORE IP Video Timing Controller - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 56271
Date Created 06/06/2013
Last Updated 06/13/2013
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2
IP
  • Video Timing Controller