The MIG 7 Series DDR3/DDR2 example design shows very low DDR3/2 bus utilization in v1.9 and v2.0 when compared to previous versions.
What is causing the low bus utilization?
A new MEM_ADDR_ORDER setting (TG_TEST) was introduced in MIG 7 Series.
Previously, BANK_ROW_COLUMN and ROW_BANK_COLUMN were the only two available settings.
TG_TEST was introduced to scramble the address going to the user interface to provide a worst case address sequence and potentially increase the address space the traffic generator accessed.
For example, the row may be remapped to the rank or column.
To increase the bus utilization, change the MEM_ADDR_ORDER parameter in the example_top.v/.vhd to either BANK_ROW_COLUMN or ROW_BANK_COLUMN.
TG_TEST is not the intended default setting for MEM_ADDR_ORDER and will be changed back to BANK_ROW_COLUMN or ROW_BANK_COLUMN (depending on the setting in the MIG 7 Series tool) in a future release.
Note: VHDL designs additionally set the MEM_ADDR_ORDER to TG_TEST in the user_design top level rtl. This should be manually modified to BANK_ROW_COLUMN or ROW_BANK_COLUMN.