We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56303

Vivado - "synth_design" in batch mode appears to be getting an incorrect file list when multiple top-level designs exist in a project


My design consists of multiple top levels that I can switch between as required when implementing portions of my overall FPGA project. I have noticed, however, that switching between these top levels works fine when using the GUI, the correct files get compiled depending on the top level chosen. However, when I use the write_project_tcl command to create a create_proj.tcl file to include in my batch script for implementing the design, it does not matter what top level is selected, Vivado tries to synthesize all files in the project. Why?


This issue can occur in batch mode if the original project contained multiple top levels, and the compile order is not reset after changing the TOP.

Add the following line after the setting of the top level in the create_proj.tcl file. For example"

set_property "top" "TopName" $obj
update_compile_order -fileset sources_1

Alternatively, avoid this issue by modifying the initial GUI project to only include 1 top level at a time. Then batch mode will work without issue after using the newly created create_proj.tcl file usingthe command write_project_tcl.

AR# 56303
Date 09/09/2013
Status Active
Type General Article
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2
Page Bookmarked