We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56307

Vivado 2013.1 - AXI protocol is not getting updated in HDL wrapper when changed on external port in IP Integrator Block design


In a simple IP Integrator design where the AXI bus is made external, with the protocol changed from AXI4 to AXI4LITE in the CONFIG settings for the port, the HDL wrapper still produces AXI4 signals and not the reduced signals expected for AXI4LITE. 

How can I address this?


First, remove the HDL wrapper. Then, in sources view, right click on the block design and Generate Output Products.

Next, close the Block design and relaunch. Finally, Re-generate the HDL wrapper and the signals should now be correct.

AR# 56307
Date 06/10/2013
Status Archive
Type General Article
  • Zynq-7000
  • Artix-7
  • Kintex-7
  • Virtex-7
Page Bookmarked