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AR# 56354

Vivado write_bitstream - ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - X out of Y logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value

Description

When generating a bitstream, the following error messages occur:

ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 3 out of 3 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. Problem ports: clk, din, dout.

ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 3 out of 3 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. Problem ports: clk, din, dout.

Solution

The error message is to notify customers that they need to set IOSTANDARD and PACKAGE_PIN, in order to protect devices from accidental damage that could be caused by the tools randomly choosing a pin location or IOSTANDARD without knowledge of the board voltage or connections.

For example:

  • If a pin is tied to ground on a board and Vivado chooses this pin as an output that is driving high, this causes contention.
  • If you have a termination scheme on the board for a pin that is the HSTL or SSTL recommended termination, and Vivado chooses LVCMOS18 (default), the signal integrity of the signal will be less than optimal.

The default I/O standard for the 7 Series is LVCMOS18 for single-ended signals for all banks. The default I/O standard was LVCMOS25 in previous architectures.


Below are possible solutions to these errors.

1. (Recommended) Add IOSTANDARD and PACKAGE_PIN constraints for all I/Os in the design.

2. If you do not care about those unconstrained I/Os, you use one of below solutions.

  • For a GUI project flow, create a .tcl file and put below two commands in it. Specify this .tcl file in the "tcl.pre" option in "Bitstream Settings". Then you can re-run "Generate Bitstream" without re-running Implementation.
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]


  • For a project mode Tcl script flow, create a .tcl file and add the following two commands to it.
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

Add the following command to your script before the "launch_runs -to_step write_bitstream" command.

    set_property STEPS.WRITE_BITSTREAM.TCL.PRE {<path_and_file_name>.tcl} [get_runs impl_1]

    • For a non-project mode Tcl script flow, add the following two commands into your script before write_bitstream command.
    set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
    set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
    • Add the following command to your XDC and re-run Implementation, no matter what flow you are using.
    set_property BITSTREAM.General.UnconstrainedPins {Allow} [current_design]

    3. If you just need to generate the bit file from the existing completed Implementation run and temporarily ignore those unconstrained I/Os, use this solution:

    • Open the Implemented design or open the routed DCP, and run the following commands in the Tcl Console:
    set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
    set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
    write_bitstream <path_and_file_name>.bit

    OR

    set_property BITSTREAM.General.UnconstrainedPins {Allow} [current_design]
    write_bitstream <path_and_file_name>.bit

    Note:

    1) In GUI project mode, when you receive these errors in bitstream generation, running the set_property commands mentioned above in the Tcl Console and then re-running "Generate Bitstream" only will NOT resolve the errors.

    This is because the properties do not get applied into the Implementation run that had already completed. When you re-run "Generate Bitstream" this Implementation run will be loaded and only the properties stored in it will be used.

    2) In some cases these DRC errors are caused by tool issues. Below are two examples where those DRC errors were caused by tool issues.

    (Xilinx Answer 63125) 2014.3 Partial Reconfiguration - Design getting DRC error on missing LOC in the 2nd configuration
    (Xilinx Answer 59742) Vivado Implementation - Incremental flow causes "Error: [Drc 23-20] Rule violation (UCIO-1)"

    Linked Answer Records

    Associated Answer Records

    AR# 56354
    Date Created 06/12/2013
    Last Updated 03/04/2016
    Status Active
    Type Known Issues
    Devices
    • Artix-7
    • Kintex-7
    • Virtex-7
    • More
    • Zynq-7000
    • Virtex UltraScale
    • Kintex UltraScale
    • Less
    Tools
    • Vivado Design Suite