The following conditions will cause this issue to occur during BSCAN testing on a pin:
There are a number of work-arounds that can be employed.
(1) Prevent FPGA configuration. This can be achieved by holding the INIT pin Low, or alternatively changing the MODE pin values if configuring from flash.
(2) Clear prior configuration using PROG pin or a power cycle and prevent re-configuration.
(3) Overwrite the FPGA configuration with a design that does not use inversion at the inputs. This can be done on a JTAG tool using an SVF file. A dummy design with some simple logic can be created and generated using compression in BitGen. This will minimize the SVF load time.
(4) Modify the original design to avoid the IOB invert path. You could identify the IOBs that use the invert path (e.g., via FPGA Editor or via inverted boundary scan values) and place the inverter in a CLB. See below for an instance of a LUT1 inverter that is placed in CLB using a UCF LOC constraint.
-- LUT1 inverter LUT1_inst : LUT1 generic map (INIT => "01") port map ( O => LED7, -- LUT general output I0 => IN7 -- LUT input );
# UCF Constraint places LUT1_inst inverter into a SLICE (versus into the IOB) INST LUT1_inst LOC=SLICE_X*Y*;
6/13/2013 - Initial release