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AR# 56380

14.5 System Generator - EDK Pcore export sets Shared Memory WRITE_MODE to READ_FIRST

Description

My System Generator model has a shared memory. When I export the EDK Pcore with dual clocks for the model, it sets WRITE_MODE to READ_FIRST for the shared memory port on the EDK side.

According to the Answer Record 34859, this may corrupt the block RAM under certain conditions. See (Xilinx Answer 34859)

Solution

This is a known issue and has been fixed in System Generator 14.6 by setting the "c_write_mode_b" to "WRITE_FIRST" when using dual clocks with EDK pcore.

A patch is available for 64-bit windows. See (Xilinx Answer 56214)

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
56214 System Generator for DSP v14.5 - Patch Update for numerous known issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34859 Virtex-6 FPGA Block RAM Design Advisory - Address Space Overlap N/A N/A
AR# 56380
Date Created 06/13/2013
Last Updated 06/13/2013
Status Active
Type General Article
Tools
  • System Generator for DSP - 14.1
  • System Generator for DSP - 14.2
  • System Generator for DSP - 14.3
  • More
  • System Generator for DSP - 14.4
  • System Generator for DSP - 14.5
  • Less