'," "Failed executing Tcl generator"">


We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56412

CORE Generator - "Failed to generate ''," "Failed executing Tcl generator"


I am attempting to generate an IP core, but errors similar to the following are occurring:

Example: Generating a PCIe v3_7

Writing VHDL instantiation wrapper for 'pcie3_7x_v1_5_0'...
WARNING:coreutil - invalid command name "5"
while executing
"$bitStringLength == 1"
(procedure "convertBitStringToHdlValue" line 12)
invoked from within
"convertBitStringToHdlValue $modelParameterValue $modelParameterDataType $modelParameterBitStringLength $language"

ERROR:sim - Failed executing Tcl generator.
ERROR:sim - Failed to generate 'pcie3_7x_v1_5_0'. Failed executing Tcl generator.

Wrote CGP file for project 'coregen'.
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'pcie3_7x_v1_5_0'. Please see the coregen log for details at '/projects/IP_cores/coregen.log'.


This error is generated when VHDL output is selected for an IP that does not support VHDL. The CORE Generator tool should be issuing a warning indicating that VHDL is not supported as a wrapper file for the selected IP and that the Verilog wrapper will be generated.

To work around this issue:

  1. Select Project Options -> Generation.
  2. Change the Design Entry option from "VHDL" to "Verilog".
  3. Generate the IP core.
AR# 56412
Date 06/14/2013
Status Active
Type Known Issues
  • ISE
Page Bookmarked