AR# 56429


2013.3 Vivado Logic Debug - Static nets connected to debug cores (ILA/VIO) in HDL are not preserved


I am connecting static nets (signals assigned constant values) to an ILA/VIO core in the HDL code in Vivado 2013.3.

These nets are not preserved after Synthesis and a mark_debug attribute is not applied.

How can I resolve this?


This issue is not seen in the 2013.4 and 2014.1 releases. 

If you encounter this issue, the workaround is to manually apply the mark_debug attribute in HDL.

AR# 56429
Date 09/04/2014
Status Active
Type General Article
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