We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56467

Vivado Synthesis - Why are some unexpected signals shown up in unassigned debug nets when the mark_debug attribute is applied on a few ports of a submodule?


in my design, The mark_debug attribute is applied on a few ports of a submodule.

However, separate to these applied ports, some unexpected signals are also shown in the unassigned debug nets in the Vivado interface.

What is the reason for these unexpected signals?


When mark_debug is applied on a few ports of a submodule, Vivado Synthesis is also applying this mark_debug property on other non-related internal nets.

These internal nets show up in the Vivado interface as unassigned debug nets.

This occurs when flatten_hierarchy is set to "rebuilt".

To work around this issue, the design can be run with flatten_hierarchy set to "none".

This issue has been fixed in Vivado 2014.4.

AR# 56467
Date 04/07/2015
Status Active
Type Known Issues
  • Vivado Design Suite
Page Bookmarked