AR# 56488


How do I perform simulation using Vivado Design Suite 2013.2 and NCSim?


The NCSim tools are not integrated into the Vivado 2013.2 Design Suite.

How do I perform simulation using those tools?



Because the NCSim tool is not integrated into the Vivado Design Suite 2013.2 release, a scripted flow must be used to perform simulation on the design and IP of the project. This answer record describes the process of performing NSCim simulation, and provides a Tcl script that can be run within Vivado tools to produce the necessary file lists for simulation compilation.


  • This script works only in the Vivado 2013.2 tools release; it does not work with prior versions of the tools.
  • This script is meant to be used with a single source and simulation set project.
  • This script cannot use the Synthesis Design Check Point IP option during output product generation.
  • For more information on IP Flows, see UG896, Designing with IP.
  • For more information on Vivado simulation, see UG900, Logic Simulation.


  • Run compile_simlib to compile the libraries and generate the library mappings in cds.lib and hdl.var.
  • Before running simulation, define the work library.


The provided script is a Tcl script to be used in the 2013.2 Vivado Design Suite. This script will perform the following actions:

  • Locates all design files in the project.
  • Locates all IP in the project and their associated files.
  • Creates a file list for NCSim simulation.

To run the script, perform the following:

  1. Open the Vivado project.
  2. Place the Tcl script in the project directory, or other convenient location. A specific location is not required.
  3. Run the Tcl script from the Tcl console with the following command: "source <path>/IES_ip_file_generator.tcl"
  4. This produces the filelist.f file in the present working directory.
  5. Use the run_behav_sim.bash as an example of how to run the NCSim simulation with the generated file list.


Associated Attachments

Name File Size File Type
ar56488_IES_ip_file_generator.tcl 3 KB TCL
ar56488_run_behav_sim.bash 606 Bytes BASH

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58890 Xilinx Simulation Solution Center - Design Assistant - Third Party Simulators - Cadence IES N/A N/A

Associated Answer Records

AR# 56488
Date 03/29/2015
Status Active
Type General Article
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