Because the VCS tool is not integrated into the Vivado Design Suite 2013.2 release, a scripted flow must be used to perform simulation on the design and IP of the project. This answer record describes the process of performing VCS simulation, and provides a Tcl script that can be run within Vivado design tools to produce the necessary file lists for simulation compilation.
- This script will only work in Vivado 2013.2 release, and will not work with prior versions of the software tools.
- This script is meant to be used with a single source and simulation set project.
- This script must use the Synthesis Design Check Point IP option during output product generation.
- For more information on IP Flows, see UG896, Designing with IP.
- For more information on Vivado simulation, see UG900, Logic Simulation.
- This script will open multiple windows to perform the file list generation as it reads the DCP to create simulation netlist for the IP.
The script provided is a Tcl script to be used in the 2013.2 Vivado Design Suite. This script will perform the following actions:
- Locates all design files in the project
- Locates all IP in the project and their associated files
- Creates a file list for VCS simulation
To run the script do the following:
- Open the Vivado project
- Place the Tcl script in the project directory, or other convenient location. A specific location is not required.
- Run the Tcl script from the Tcl console with the following command: source <path>/get_vcs_sim_files_RTL_proj.tcl
- This will produce the filelist_vcs.f file in the present working directory.
- Use the vcs.bash as an example of how to run the VCS simulation with the generated file list.