AR# 56492

2013.2 Vivado IP Flows - Simulation fails with "ERROR: [VRFC 10-2063] Module not found while processing module instance []"


In 2013.2 Vivado Integrated Design Environment, I am attempting to run functional simulation on a design that contains IP cores.

When I run simulation from the Vivado Integrated Design Environment, I get the following error message:

ERROR: [VRFC 10-2063] Module <core_name> not found while processing module instance <inst_name> [<file location>]

Simulation will fail when using Vivado Simulator or ModelSim/Questa simulator from the Vivado integrated design environment.

What is causing this error?


As the error message suggests, the Simulator does not find the needed file required for simulation of an IP core.

This error will occur in Vivado 2013.2 tools if the Generate Synthesized Design Checkpoint option is checked during the IP generation process. This option creates a Design Check Point (DCP) file for the generated IP core in addition to the standard generated files. This DCP file is a pre-synthesized version of the IP core which will be used during synthesis and implementation in place of the RTL files for the IP core. The problem occurs in Simulation because the correct files for the IP core will not be passed to the simulator.

To confirm this is the reason for the error, check to see if the Hierarchy tree shows the IP core with an orange box as shown in the following image:


  • A tactical patch to resolve this issue is attached to this answer record. Apply the patch for the operating system according to the instructions contained in the readme file in the patch archive.



  • To avoid the error without the patch being installed, follow these steps:
    1. Right-click on the module and select Unset Out-Of-Context Module...
    2. Click OK on the next dialog box that comes up asking to remove the results.
    3. Do this for all the IP cores that have been marked as Out-Of-Context (orange). Multiple IPs can selected at the same time.
    4. Re-run the simulation step again and confirm the simulation is working
  • To avoid this error, do not check the Generate Synthesized Design Checkpoint option when generating the IP cores.

Do not select this option until you have finished functional verification of your design and you are moving to the implementation stage.


Associated Attachments

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58882 Xilinx Simulation Solution Center - Design Assistant - Vivado Simulator - Behavioral Simulation N/A N/A
AR# 56492
Date 03/24/2015
Status Archive
Type Known Issues