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AR# 56494

Vivado Synthesis - ERROR: [Synth 8-1766] cannot open include file .v


I define macros in the include.v file, add this file to project sources and refer to this file with the include statement in other source files:
'include include.v
I have set the include.v file as global included.

However, I still received the following error.

ERROR: [Synth 8-1766] cannot open include file include.v

How can this be resolved?



You can use one of the following 2 methods.

1. Set the include.v file as global included and set its file_type to "Verilog Header".

If file_type is not set to Verilog Header, the include file will be treated as an ordinary Verilog file which can be referred by the other Verilog files and this causes the error above.

set_property file_type "Verilog Header" [get_files ../source_inclu/include.v]
set_property is_global_include true [get_files ../source_inclu/include.v]

2. Do not add the include.v file into project sources or read the include file in non-project mode.
Set the include_dirs option to the location of the include.v file in the synth_design command or Synthesis settings.

synth_design -top top -part xc7k70tfbg484-2 -include_dirs {../source_inclu}

Please refer to (Xilinx Answer 54006) for more information about include file settings.
AR# 56494
Date 07/30/2014
Status Active
Type General Article
  • Vivado Design Suite
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