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AR# 56512

14.6 EDK, Zynq-7000 - How do I connect custom AXI HDL outside of EDK XPS to a Zynq AXI interface?


I would like to connect my custom AXI master or slave to a Zynq AXI interface, but prefer to manage the HDL outside of XPS. How do I accomplish this?


The following example is used to add an AXI4-Lite custom IP to Zynq AXI_GP0 on a ZC702 board, using PlanAhead tool to manage the custom AXI.

Note: The resulting PlanAhead 14.5 project is attached below. To use, run the "hello world" application in SDK workspace to demonstrate the access of the peripheral from an ARM CPU.
1. Create a new PlanAhead project based on ZC702 board, create an XPS submodule and open it.
2. Double click IP Catalog -> Utility -> AXI External Slave Connector to add an axi_ext_slave_conn IP. The external AXI connectors break out the AXI interface "BUS" data types into individual signals. They also provide a place to apply required metadata associated with the slave to the AXI Interconnect to be added later. See the AXI Interconnect Product Guide and the AXI Reference Guide for more information on these settings.
3. In the XPS Core Config Wizard, click the System tab and modify the Slave AXI Protocol to AXI4Lite. Set any other characteristics of the slave to match the custom IP, such as Data Width, AXI Acceptance or Issuance (the number of outstanding transactions that the slave can accept or a master can generate), or variable port width parameters.

4. Then click OK until you successfully add the axi_ext_slave_conn IP.
5. Allow automatic connections by the XPS tool popup. This automatically adds an AXI_GP0 -> axi_interconnect -> axi_ext_slave_conn AXI interface connection and also makes the external_axi_if signal group external to XPS. These 'external' signals will become part of the XPS instantiation in the parent PlanAhead project. A default address range is also chosen for the slave that can be accessed from other AXI masters in XPS such as a CPU.
6. Check the automated and external connections.  Please refer to the following pictures:

7. Select the ACLK and ARESET_N signals for the custom slave and make them external to allow consumption by the slave in PlanAhead tool. For this project, select the FCLK_CLK0 and M_AXI_ARSET_OUT_N of axi_interconnect and right-click Make External.
8. Consider running Hardware- > Generate Netlist to perform DRCs on the XPS design. When satisfied, close XPS.
9. Right-click the XPS icon in PlanAhead and select Create Top HDL. Open the resulting file and notice the AXI external connector signals that were exposed.

10. Add/Create custom IP code sources to PlanAhead project. Collections of example AXI cores are available in (Xilinx Answer 37425). The HDL files contained in these cores can be extracted to be used as a starting point.
11. Modify the top-level HDL to instantiate the custom AXI peripheral, and connect to the external connector signals on the XPS instantiation. Note that the various *ID signals change in width as the bus topology in XPS is modified.
12. Save the top-level HDL file and continue with design flow, such as generating a bitstream.


Associated Attachments

Name File Size File Type
zc702_axi_ext_slave.rar 4 MB RAR
AR# 56512
Date 10/27/2017
Status Active
Type General Article
  • Zynq-7000
  • PlanAhead - 14.5
Boards & Kits
  • Zynq-7000 SoC ZC702 Evaluation Kit
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