UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56539

2013.2 - Vivado IP Integrator - Bus interface property ID_WIDTH mis-match when mig_7series IP is connected to an AXI Interconnect

Description

In the Vivado IP Integrator system, if the mig_7series IP is connected to the AXI Interconnect, the system will return an error during validation similar to the following:

BD 41-237] Bus Interface property ID_WIDTH does not match between /mig_7series_1/S_AXI(1) and /axi_interconnect/xbar/M00_AXI(2)

How can I address this?

Solution

To fix this issue, the user needs to re-customize the mig_7series IP and set the width equal or greater than the interconnect interface.

In the example shown in the above error message, the value needs to be set to 2.

An example snapshot is shown below in the AXI Parameter options:

 


 

The MIG ID width propagation was fixed in Vivado 2013.3.

AR# 56539
Date 09/07/2017
Status Active
Type General Article
Devices
  • Zynq-7000
  • Artix-7
  • Kintex-7
  • Virtex-7
Tools
  • Vivado Design Suite - 2013.2
IP
  • MIG 7 Series
Page Bookmarked