UPGRADE YOUR BROWSER
We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
ERROR: [Place 30-137] Unroutable Placement! A GT / BUFR component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the BUFR if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the CELL.NETs used in this clock placement rule is listed below. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets iof_sgmii_pchgbe0/inst/transceiver_inst/gtwizard_inst/gt0_rxoutclk_i] >
iof_sgmii_pchgbe0/inst/transceiver_inst/gtwizard_inst/GTWIZARD_i/inst/gt0_GTWIZARD_i/gthe2_i (GTHE2_CHANNEL.RXOUTCLK) is locked to GTHE2_CHANNEL_X1Y28
iof_sgmii_pchgbe0/inst/transceiver_inst/gtwizard_inst/rxrecclkbufmr (BUFMR.I) is provisionally placed by clockplacer on BUFMRCE_X1Y12
AR# 56600 | |
---|---|
Date | 03/25/2015 |
Status | Active |
Type | Error Message |
Tools |
|