In a simple Vivado IP Integrator system with a mig_7series, the IP connects to an external AXI interface via an AXI Interconnect.
However, during Generate Output Products, I am seeing an error similar to the following:
How can I fix this issue?
This error indicates that the IP does not know the relationship between the AXI Interconnect S00 ACLK and the MIG's ui_clk.
The ui_clk is the DDR clock /2 or /4 depending on the MIG configuration.
If you use the ui_clk output to drive the other AXI clocks on the Interconnect, the design should validate successfully.
However, in this case the ACLK on the interconnect's external interface properties need to be updated to include the correct clock domain.
To do this highlight the S00_ACLK, and in the AXI External Interface Properties add the correct domain:
The CLK_DOMAIN can be obtained by clicking on the ui_clk pin and viewing the properties.