AR# 56644

2013.2 - Vivado IP Integrator - [Project 1-486] Could not resolve non-primitive black box cell 'design1_mig_7series_1_0'

Description

In a simple IP Integrator design containing a MIG 7series IP, an error message similar to the following occurs when I run synthesis in the Vivado tool:

netlist_1open_run synth_1 -name netlist_1
[Designutils 20-1281] Could not find module 'mb_design_mig_7series_1_0'. The XDC file C:/project/mb_system/mb_system.srcs/sources_1/bd/mb_design/ip/design1_mig_7series_1_0/design1_mig_7series_1_0_board.xdc will not be read for this module.
[Project 1-486] Could not resolve non-primitive black box cell 'design1_mig_7series_1_0' instantiated as 'mig_7series_1' ["C:/project/mb_system/mb_system.srcs/sources_1/bd/design1/hdl/mb_design.vhd":4951]

How can I address this issue?

Solution

In the Vivado tool, under Sources:

  1. right-click the block design and select Reset Output Properties as shown below:

  2.  

  3. Next, change the Project Settings, Target language to Verilog. Click Apply and OK:

    lang_settings.png
    lang_settings.png
  4.  

  5. Finally, run Generate Output Products again:

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Associated Answer Records

AR# 56644
Date 10/21/2013
Status Archive
Type General Article
Devices More Less
Tools
IP