We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 56682

MIG 7 Series QDRII+ - Write Calibration might fail for x18 multiple component designs when K/K# is not located in the same byte lane as write data


Version Found: v2.0
Version Resolved: See (Xilinx Answer 54025)

A Write Calibration update is required for MIG 7 Series QDRII+ designs due to potential calibration failures when centering data not located in the same byte lane as the K/K# clock. Single components are not affected by this issue. 


For x18 multi-component designs (i.e., 36-bit data width, 2 x18 components), Write Calibration is not performed for write data not located in the same byte group as K/K# of the first component. Instead of performing calibration for this data group, the algorithm jumps to the second component and eventually fails during Write Calibration.

To work around the Write Calibration issue, the attached patch must be applied.

Note: Instructions for applying the patch for Vivado, ISE, and EDK users can be found in the readme.txt file located in the patch ZIP.

Revision History
08/16/2013 - Updated patch with latch fix from (Xilinx Answer 57148)
07/11/2013 - Initial release


Associated Attachments

Name File Size File Type
AR56682.zip 45 KB ZIP

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 56682
Date 08/29/2013
Status Active
Type Known Issues
Page Bookmarked