The DDR3 SODIMMs specified on the 7 series evaluation kits (including the VC709) are JEDEC 204 Pin SODIMM compliant.
However, we also have two extra pins defined as mounting TABs (described by the SODIMM Connector Data Sheet) and 18 pins for the SODIMM EMI cage / shield which are required for EMI mitigation during CE testing.
Per the schematics symbol, the extra pins are assigned as pins 205 - 225 (two as TABx and 18 as SHLDx) as shown below:
Answer Number | Answer Title | Version Found | Version Resolved |
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51901 | Virtex-7 FPGA VC709 Connectivity Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
AR# 56695 | |
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Date | 07/05/2013 |
Status | Active |
Type | General Article |
Boards & Kits |