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AR# 56706

LogiCORE Video Scaler v8.0 - Why do I get a simulation error "Index X out of bound X downto X" when attempting to simulate the Video Scaler?


Errors similar to the following occur when I run behavioral simulation using the Video Scaler v8.0:

FATAL_ERROR: Index 102 out of bound 101 downto 0
Time: 399611250 ps  Iteration: 1  Process: /top_tb/uut/scaler0/U0/Scaler1/Scaler_RTI_inst/Scaler_wrap0_inst/Scaler_wrap0_core_u/scaler_top_inst/generateconfig4/Inst_scaler_Y/LineBuff/linebuf1/generatedoutreadfirstb/line__309
  File: c:/scaler_test/scaler_test.srcs/sources_1/ip/scaler/v_scaler_v8_0/hdl/vhdl/MemXLib_arch.vhd
Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
Time: 1125 ns  Iteration: 0  Process: /tb_v_scaler_0/uut/U0/Scaler1/Scaler_RTI_inst/Scaler_wrap0_inst/Scaler_wrap0_core_u/scaler_top_inst/generateconfig1_3/Inst_coefmem/generatefixedcoeframs/CoefMem/generatedoutreadfirsta/line__210      File: /scaler_sim/project_1/project_1.srcs/sources_1/ip/v_scaler_0/v_scaler_v8_1/hdl/vhdl/CoefRAM.vhd
@             1510000 : [AXI-S Video Slave  1] set to Passive Mode ...
@             1510000 : CE Generator : Enabled (always asserted)
@             2010000 : [AXI-S Video Master 1] STARTED
@             2010000 : [AXI-S Video Slave  1] STARTED
ERROR: Index 2560 out of bound 2559 downto 0
Time: 56345 ns  Iteration: 0  Process: /tb_v_scaler_0/uut/U0/Scaler1/Scaler_RTI_inst/Scaler_wrap0_inst/generatesingleinputbuffer/ScalerInObjFIFO/memory0/generatedoutwritefirstb/line__2487
  File: /scaler_sim/project_1/project_1.srcs/sources_1/ip/v_scaler_0/v_scaler_v8_1/hdl/vhdl/MemXLib_arch.vhd
HDL Line: /scaler_sim/project_1/project_1.srcs/sources_1/ip/v_scaler_0/demo_tb/tb_v_scaler_0.v:327


This is a known issue that can occur in some configurations of the Video Scaler and will be fixed in a future release of the tools.

This is a simulation only issue, and does not affect implemenation. Users can still successfully implement a working bitstream that can be run in hardware.

There are two ways to work around this issue:

  • Use post-synthesis functional simulation.
  • Back-annotate the behavioral simulation with a structural simulation model for the Scaler (use write_vhdl/write_verilog tcl commands).
    In Vivado 2013.3 or later tools, a v_scaler_0_funcsim.v.vhdl is automatically generated when the user generates the DCP file. A user can replace the simulation files for the Video Scaler with the v_scaler_0_funcsim.v/vhdl file. The easiest way to do this is to create a new simulation set and specificy the test bench files and the v_scaler_0_funcsim.v/vhdl (rather than using the xci file).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54540 LogiCORE IP Video Scaler - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 56706
Date 11/25/2013
Status Active
Type General Article
  • Video Scaler
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