When carrying out Boundary Scan testing, I observe that there is additional power drawn by the device when the SAMPLE instruction is loaded.
Why is this extra current drawn by the FPGA?
To carry out Boundary Scan testing, SelectIO pins and GT pins need to be set up.
The additional current consumed will not exceed the current consumed in normal user operation. The current consumed is not documented as it will not be higher than normal operation and is not a risk for the device.
In UltraScale, the GT Quad power can be controlled via specific boundary-scan cells that can be found via the diff of "safe values" between the PRODUCTION and ES2 BSDL files.
Modifying these bits between 0 (ON) or 1 (OFF) results in the boundary-scan test vectors that keep the GT enabled/disabled. The consequence of disabling it is that the GTs are disabled and boundary-tests on the GT pins would not work.