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AR# 56775: Why do I see additional power consumption when I attempt Boundary Scan testing?
Why do I see additional power consumption when I attempt Boundary Scan testing?
When carrying out Boundary Scan testing, I observe that there is additional power drawn by the device when the SAMPLE instruction is loaded.
Why is this extra current drawn by the FPGA?
To carry out Boundary Scan testing, SelectIO pins and GT pins need to be set up.
For SelectIO pins, the SAMPLE instruction will force the input buffer to LVCMOS. If the input level is floating between the rails for LVCMOS (without a pull-up), then additional current draw can be seen.
For GT pins, the SAMPLE instruction will turn on the band-gap and pad driver to get ready for AC-JTAG (IEEE 1149.6) operation. This will increase power consumption for an unconfigured device, as the GT will be in power down mode.
If the power supplies are sized only for a small number of GTs, this additional power can be a problem.