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AR# 56803

Example Design on IBERT Core is not getting implemented successfully


If I attempt to implement an IBERT core example design, the following message appears and the refclk signals are not routed:

Net: refclk0_i is not completely routed
Net: refclk1_i is not completely routed


To resolve this issue, add the assignments below in the top file (i.e., example_ibert_7series_gth_0.v/vhd).

assign gtrefclk0_i[1] = refclk0_i[0];
assign gtrefclk1_i[1] = 1'b0;


Also, modify the LOC constraints of the IBUFDS_GTE2 primitive to the appropriate locations in the XDC file.

A CR has already been filed to address this issue.

AR# 56803
Date 07/18/2013
Status Active
Type Known Issues
  • Virtex-7
  • Virtex-7Q
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2
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