To improve runtime for timing driven implementation, the PAR command line defaults for the Virtex, Virtex-E, and Spartan-II families in M2.1i have changed to NOT run Cost Based and Delay Based Clean-up passes. Because of this change, you may notice lower design performance results from PAR when targeting these families. This will occur on designs that are run in M2.1i with no timing constraints applied (non-timing driven).
To get a more "realistic" estimate of how your design will perform without any timing constraints applied, please follow this recommendation:
1. Implement your design until PAR has completed. 2. Open up the Flow Engine on your (Routed,OK) revision. 3. Under Setup-> FPGA Re-entrant Route, specify the number of clean-up passes to be run. 4. Click OK 5. In the Flow Engine, select Flow->Step Back 6. Select Flow->Run
Check the Reports Browser (P&R Report/Post Layout Timing Report) for improved performance results.