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AR# 56861

Vivado Synthesis - ERROR: [Synth 8-1032] xxx is not declared in yyy


If vhdl entity is instantiated by library reference (without explicit component declaration) and the library name is equal to an entity name that exists in this library, the following error message can occur in vivado synthesis:

Error: [Synth 8-1032] user_logic is not declared in dma_sm.


Example dma_sm.vhd:

library dma_sm;
use dma_sm.user_logic;

entity dma_sm is


USER_LOGIC_I : entity dma_sm.user_logic




To work around this issue, rename either the library or the entity so that the library name is not the same as any entity name in it.
AR# 56861
Date 01/21/2015
Status Active
Type General Article
  • Vivado Design Suite
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