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AR# 56961

Vivado Simulator: How to read files in VHDL or Verilog code using Relative Paths?

Description

When I try to open a file with the following snippet using relative addressing, the error message below is received:

stim_proc: process

  FILE feventlist: TEXT OPEN Read_MODE is "sorted_ecoli_events.txt";


Vivado Simulator 2013.2
FATAL_ERROR: File sorted_ecoli_events.txt could not be opened
on HDL file C:/Users/ukplmtgi/Documents/Work/Vdesigns/ColumnLogic/Col_tb.vhd line 195
ERROR: [Simtcl 6-50] Simulation engine failed to start: The Simulation shut down unexpectedly during initialization.
Please see the Tcl Console or the Messages for details.
ERROR: [Vivado 12-2332] Received fatal error while launching XSIM application!
ERROR: [Simtcl 6-50] Simulation engine failed to start: The Simulation shut down unexpectedly during initialization.
Please see the Tcl Console or the Messages for details.


If absolute addressing is used it works without any issue:

stim_proc: process

  FILE feventlist: TEXT OPEN Read_MODE is "C:/Users/ukplmtgi/Documents/Work/Vdesigns/ColumnLogic/sorted_ecoli_events.txt";



Solution

To work around this issue follow the steps below:

Example:

file my_input : TEXT open READ_MODE is "file_io.txt";

Steps: 

1. Click on "Add Sources".

2. Select "Add or Create Simulation Sources".

3. Select all of the .txt files which are required to be read or used in your project and click OK.

4. Ensure "Copy Sources into Project" and "Include all design sources for simulation" are selected.

5. Click on finish.

6. These files will be added to the project.

The files will now open properly even with relative paths.


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58882 Xilinx Simulation Solution Center - Design Assistant - Vivado Simulator - Behavioral Simulation N/A N/A
AR# 56961
Date Created 08/01/2013
Last Updated 09/04/2014
Status Active
Type General Article
Devices
  • Kintex-7
Tools
  • Vivado Design Suite - 2013.2