2. Support
  3. AR# 5697: SYNPLIFY: Using FDCE or FDPE support for 9500 synthesis
  4. AR# 56975: Virtex-7 FPGA Gen3 Integrated Block for PCI Express v2.1 - Field to set "VF Device ID" in PF1 SRIOV Config tab of GUI is grayed out

AR# 56975

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Virtex-7 FPGA Gen3 Integrated Block for PCI Express v2.1 - Field to set "VF Device ID" in PF1 SRIOV Config tab of GUI is grayed out

Description

Version Found: v2.1
Version Resolved and other Known Issues: (Xilinx Answer 54645)

I am configuring a Virtex-7 FPGA Gen3 Integrated Block for PCI Express v2.1 core in Vivado Design Suite.

However, the field to set "VF Device ID" in the PF1 SRIOV Config tab is grayed out in the GUI.

Solution

This is a known issue scheduled to be fixed in a future release of the core.

To work around this issue, assign the required value manually in the source file.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
 
Revision History:
08/04/2013 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54645 Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 56975
Date 10/16/2014
Status Active
Type Known Issues
IP
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