Version Found: MIG 7 Series v2.0 Rev 1
Version Resolved: See (Xilinx Answer 54025)
When building a MIG 7 Series core in the Vivado tool, the Generate Output Products window that appears after an IP core is built now contains the Generate Synthesized Design Checkpoint (.dcp)" checkbox option.
If this option is selected and the resultant .dcp file is used in place of the MIG RTL, the following type of error is encountered:
ERROR: [Synth 8-3438] module 'mig_7series_0' declared at 'c:/0_dcp_flow/project_1/example_project/mig_7series_0_example/
mig_7series_0_example.runs/synth_1/.Xil/Vivado-3976-/realtime/mig_7series_0_stub.v:7' does not have any parameter 'MEM_TYPE' used as named parameter override ["c:/0_dcp_flow/project_1/example_project/mig_7series_0_example/mig_7series_0_example.srcs/sources_1/imports/rtl/example_top.v":467]
The 7 Series MIG core does not support the DCP/OOC (Out of Context) flow. By default, this option is available for all IP. However, this flow does not work for MIG and will produce errors similar to the one above if the MIG .dcp file is used.
The full RTL must be used when instantiating a MIG core in a design. Refer to (Answer Record 54025) for when DCP/OOC support will be added for MIG 7 Series IP.
08/07/2013 - Initial release
11/12/2013 - Updated to clarify DCP/OOC support
01/31/2014 - Updated and added to release notes