You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
2014.4 Vivado IP Integrator - AXI ports from Vivado CPRI do not match IP Integrator AXI external ports
If I make the AXI signals external in the IP Integrator block design, the resulting AXI signals do not match the CPRI IP AXI interface signals.
CPRI_MST_M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 ); //From IPI
s_axi_arready : OUT STD_LOGIC; //From CPRI IP
This causes potential synthesis issues.
To address this issue, please consider one of the following work-arounds:
- Set the Target Language to Verilog in the Project Settings, instead of VHDL.
- To do this, click Project Manager -> Project Settings and change the Target Language to Verilog.
- If you want to use VHDL:
- You must perform bit slicing in the external HDL code.
- Ensure that there is a coupler present, for example by turning on a register slice.
Was this Answer Record helpful?