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AR# 57079

7 Series - Configuration - BPI Synchronous Burst Read Mode, are the parameters with respect to CCLK at the pin?


7 series FPGAs Data Sheets: DC and Switching Characteristics (DS181 [v1.6], DS182 [v2.4], and DS183 [v1.16]) specify timing parameters for BPI Synchronous Burst Read Mode. In these data sheets, it is not specified where the data setup time specifications are with respect to CCLK. (i.e. is this with respect to the CCLK edge coming at the pin of the FPGA or with respect to CCLK internal to the FPGA).

Where is the timing with respect to CCLK?


The specifications are with respect to the external CCLK pin. This will be updated in a future version of the Data Sheets.
AR# 57079
Date 08/20/2013
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
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