SYNPLIFY - "xcmap.c: Error: primitive view:PrimLib.z(prim) not handled yet"
General Description: When synthesizing through Synplify, the following error "xcmap.c: Error: primitive view:PrimLib.z(prim) not handled yet" is reported.
This is an obscure error message that indicates an user error. The error occurs if the top-level is defined as a black-box and is not declared anywhere else as a submodule.
Synplify compiles the last module as the top level module for Verilog. For VHDL, the last entity/architecture in the last file is the top level. The user should look at the "Source Files" list or the top. Please see (Xilinx Solution 1061). Does the last file listed contain the top level module or entity/architecture pair?