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AR# 57127

Vivado Simulator - Post Synthesis and Post Implementation Timing simulation options are greyed out in my VHDL Vivado project, how can I run VHDL timing simulations?


My design flow requires both post synthesis and post implementation timing simulations to be run as part of our verification process.

I have a VHDL only Vivado project and only have a VHDL simulator license for my 3rd party simulator.

How can I run the VHDL timing simulation?


Post Synthesis and Post Implementation Timing Simulations are not supported for VHDL in Vivado. 

There is a note in UG900, "Logic Simulation User Guide" outlining this.

"IMPORTANT: Post-Synthesis and Post-Implementation timing simulations are supported for Verilog only. There is no support for VHDL timing simulation."

A suggested workaround for this was to run the "write_vhdl" and "write_sdf" commands from the Tcl Console and run the simulation in your 3rd party simulator standalone.

However this will not work as "write_sdf" will not align to the VHDL netlist because write_vhdl does not support "-timesim" that is needed for timing simulation.

Possible workarounds:

  1. If you have a mixed language 3rd party simulator license, it is possible to modify the Vivado project settings to Verilog and run the post synthesis and post implementation timing simulations in Verilog.
    The project can still be VHDL source but the simulation netlist will be Verilog.
    Note: In future releases it might be possible that for a VHDL project, instead of graying out the post synthesis and implementation timing option, a Verilog option will be available to run provided the customer has a valid license.
  2. Alternatively, if you do not have a 3rd party mixed langauge simulator license, modify the project settings to use Vivado Simulator which is mixed language and included in your Vivado license.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58882 Xilinx Simulation Solution Center - Design Assistant - Vivado Simulator - Behavioral Simulation N/A N/A
AR# 57127
Date 09/05/2014
Status Active
Type General Article
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2