AR# 5713


pld_men2edif - "ERROR:basnu:120 - logical net "port_signal_name" has multiple pad connections "


When I attempt to run "pld_men2edif' the following error occurs: 


"ERROR:basnu:120 - logical net "port_signal_name" has multiple pad connections" 


What could be causing this error?


This error can occur while running pld_men2edif when there are special ports such as TDO, MD0, MD1, TDI, etc., used in the schematic for user I/O after configuration, and a symbol was created for a Board Level Simulation where the symbol has a pin on it the same name as the signal name going to the special PORT pad (i.e., TDO). 


It is understandable why users would want to have the signal going to the TDO pin for user I/O to go to the symbol pin for Board Level Simulation. The problem arises because the TDO pad is special, as well as MD0, MD1, etc. Typically, for IPADs and OPADs when pld_men2edif is run, the PADs are not written into the EDIF netlist, as it is not required. Running pld_men2edif translates the signal going to the PAD to a "port" in the netlist so that the Xilinx tools will be able to determine if this goes to an I/O pin or not. For special pins, like TDO, the specific pad must be written into the netlist for the Xilinx tools to be able to realize that this particular signal going to the TDO in the schematic must only go to the TDO pin on the package. 


When a symbol resides under the top level schematic EDDM, in which this symbol does contain a pin for the signal going to the TDO pad, pld_men2edif creates a netlist that essentially has two ports driving a single buffer; one going to a "port" in the netlist, and the other going to the TDO pad in the same netlist. 


You might be asking, "Why does pld_men2edif complete without errors for my top level schematic that only has IPADs and OPADs?", even though you do have a symbol created for a Board Level Simulation with these signals going to pins. The reason this works is that there is a property called CLASS=P on IPADs and OPADs which causes pld_men2edif to not write the IPAD and OPAD elements into the resulting EDIF netlist, and to write "port" statements for them instead. The CLASS=P property also makes the signal hierarchial, which is why the symbol for the top level schematic can contain pins for the signals going to all the IPADs and OPADs. Due to the nature of the property the CLASS=P property cannot be used on special pins such as TDO, as this results in a multiple drivers error. 


NOTE: This is not a problem for a Baord Level Timing Simulation, and only arises for a Board Level pre-M1 Functional Simulation.


There are two ways to work around this problem that requires a little effort. However, you must be careful to keep things in sync. 


1) Maintain two seperate designs, one for implementation, and one for functional board level sim. Within 1) there are two ways to do this: 

a. add a portout to the existing schematic in parallel with the TDO  

b. add an OPAD in parallel to the TDO. Making sure in both of the above the symbol for the board schematic exists only in the functional sim design. The Board Level schematic viewpoint can then point to the "copy" of the design. However, any design changes need to be updated in the "copy". 


2) Create a symbol in the functional board level sim directory, that represents the chip. Then create a new empty sheet under this and copy and paste only the top level sheet of the chip design, and paste this into the new empty sheet. This schematic now has to be modified as in 1), but will leave the original design untouched for implementation. Any design changes in the original top level schematic need to be updated in the Board Level Simulation top level schematic.

AR# 5713
Date 05/14/2014
Status Archive
Type General Article
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