Version Found: v2.0
Version Resolved: See (Xilinx Answer 54025)
All MIG QDRII+ 7 Series v2.0 designs infer a latch for signal init_rd_cmd_d_reg inside phy_write_init_sm.v.
This should not affect hardware results as the timing for this path should have sufficient margin. However, the attached latch_timing_force_check.tcl script can be run on your design to check if timing is an issue. If so, the attached patch (AR57148.zip) can be applied to resolve the latch inference.
NOTE: Instructions for applying the patch for Vivado can be found in the readme.txt file which are located in the patch ZIP.
08/16/2013 - Initial release